1. Technical Field
This invention generally relates to dynamic memory devices, and, more particularly, this invention relates to a sense amplifier circuit for a dynamic random access memory formed as a single integrated circuit device.
2. Description of Related Art
Numerous dynamic random access memories (DRAMs) are known in the related art. Typically, DRAMs are manufactured using arrays of single-transistor memory cells. To achieve the best results, the single-transistor cells are fabricated as metal-oxide semiconductor field effect transistors (MOSFETs) on a single silicon substrate. Each MOSFET is connected to a small capacitance that stores an electric charge. Usually, a logical "1" is represented by the presence of a charge on the storage capacitance, and a logical "0" is represented by the lack of a charge on the storage capacitance.
Since the charge stored on the storage capacitance gradually leaks, information must be periodically rewritten before the charge leaks out completely. This operation is commonly referred to as "refreshing" the memory cells. The frequency at which the cells need to be refreshed depends on the rate of leakage of the MOSFET.
DRAMs include a plurality of bit lines that are used to sense or read information stored in the cells and to write information into the cells. The bit lines interconnect with respective word lines that are shared by all of the memory cells in each row. The MOSFETs are connected between the word lines and the storage capacitances to selectively provide access to the information stored by the capacitances. Thus, these MOSFETs are commonly referred to as access transistors. When a selected word line is enabled, the data from each memory cell in the selected row is coupled to the respective bit lines through the access transistors.
The bit lines are connected in pairs to a differential sense amplifier. Prior to the selection of a cell, the bit lines are brought to equal potentials, i.e., equilibrated, by n-channel MOSFET transistors. The gate of the equilibrate transistor is turned off, and, then, one of the pair of bit lines is coupled to a selected cell. The sense amplifier compares the charge on the cell's storage capacitance to the charge on the other bit line. The sense amplifier receives the differential voltage between the pair of bit lines, and amplifies the differential voltage to produce a signal representative of the logical state of the memory cell connected to the selected bit line. At the same time, the sense amplifier also refreshes the storage capacitance.
Conventionally, in DRAMs each sense amplifier pulls its respective bit line to circuit ground through one or two transistors. If two transistors are used, the first transistor to be turned on is small so that the sense amplifier begins to amplify slowly. Then, a second, larger transistor is turned on so that the sense amplifier amplifies quickly to discharge the bit line to ground. In addition, the gates of the unselected access transistors in the memory cells are normally at ground potential when turned off. Therefore, the resistance of the access transistors must be sufficiently high to ensure no leakage through the transistors to their associated bit lines which have been drawn to ground. The problem is that the threshold voltage that must be applied to the gates of the access transistors is quite high. Therefore, the time necessary for the gate voltage on the word lines to ramp from ground to the threshold voltage reduces the speed of the memory. Also, as memory cells decrease in size to increase the density of the memory, it becomes more difficult to keep the access transistors turned off due to the device physics of n-channel MOSFETS.